applications
mobile phones
PC multimedia
digital still camera
toys/games
OV5630/OV5633
ordering information
OV05630-V58A
(color, 58-pin CSP2)
OV05633-C48A
(color, 48-pin CLCC)
OV05630-G04A
(color, chip probing, 200 μ m backgrinding,
reconstructed wafer)
product features
product specifications
OmniPixel3-HS technology
optical size of 1/3.2"
automatic image control functions:
– automatic exposure control (AEC)
– automatic band filter (ABF)
– automatic 50/60 Hz luminance
detection
– automatic black level calibration
(ABLC)
programmable controls for: frame
rate, AEC/AGC, mirror and flip,
cropping, windowing and panning
image quality controls: lens
correction, defective pixel canceling
support for video or snapshot
operations
support for internal and external
frame synchronization
support for LED and flash strobe
mode
support for horizontal and vertical
sub-sampling
digital video port (DVP) parallel
output interface
MIPI interface (two lanes), MIPI
hub/secondary camera interface
embedded one-time programmable
(OTP) memory
on-chip phase lock loop (PLL)
embedded 1.5V regulator for
core power
programmable I/O drive capability
supportforblacksuncancellation
High Dynamic Range (HDR) ready
for sub-sampling resolution
providing a dynamic range of ~80dB
active array size: 2592 x 1944
power supply:
– core: 1.5VDC± 5%
– analog: 2.6 ~ 3.1V (2.8V typical)
– I/O: 1.7 ~ 3.1V
temperature range:
– operating: -30° to 70°C
– stable image: 0° to 50°C
output format:
– 10-bit RGB RAW output
– I/O tri-state configurability
lens size: 1/3.2"
lens chief ray angle: 25 ° non-linear
input clock frequency:
6~27 MHz
shutter: rolling shutter
max image transfer rate:
– QSXGA: 15 fps
– 1080p: 30 fps
– 720p: 60 fps
– VGA (640x480): 60 fps
– 1280x960: 60 fps
dynamic range: ~ 80 dB
pixel size: 1.75 μ m x 1.75 μ m
package/die dimensions:
– CLCC: 14.22 mm x 14.22 mm
– CSP2: 6385 mm x 6285 mm
– COB: 6400 mm x 6300 mm
standard serial SCCB interface
functional block diagram
OV5630 / OV5633
analog
digital (DVDD)
array and
analog
process
A/D
converter
AEC/AGC
BLC
(ADC stage)
sensor
timing
control
frame
average
digital
BLC
DSP
interface
ISP
DVP
para
port
power
control
note 1
digital: DIO_VDD
MIPI
PHY
PLL
windowing
note 3
sensor
control
note 2
register
set
SCCB
slave
note 1 power control (positive and negative pump, regulator)
note 2 sensor control (group hold, mask corrupted frame, etc.)
note 3 windowing (crop, mirror, vflip, etc.)
5630_PB_1
4275 Burton Drive
Santa Clara, CA 95054
Version 1.11, August 2008
tel: +1 408 567 3000
fax: +1 408 567 3001
www.ovt.com
OmniVision reserves the right to make changes to their products or to discontinue any
product or service without further notice. OmniVision and OmniPixel are registered
trademarks of OmniVision Technologies, Inc. The OmniVision logo, CameraChip and
OmniPixel3-HS are trademarks of OmniVision Technologies, Inc. All other trademarks
are the property of their respective owners.
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